Memory device with predetermined start-up value

ABSTRACT

A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising; exposing a pattern on a wafer for creating structures for a plurality of memory cells for the semiconductor memory device, wherein the pattern is exposed by means of one or more charged particle beams; and varying an exposure dose of the one or more charged particle beams during exposure of the pattern to generate a set of one or more non-common features in one or more structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to International Application No.PCT/JP2018/032518, filed Aug. 28, 2018, and published as WO 2019/045087A1, which claims priority of U.S. Provisional Application No. 62/550,727filed on Aug. 28, 2017. The contents of these applications are eachincorporated herein by reference in their entireties.

TECHNICAL FIELD

The disclosed embodiments relate to a memory device. More specifically,the disclosed embodiments relate to a semiconductor memory device havinga predetermined start-up value.

BACKGROUND

Semiconductor memory is typically formed from a large array of memorycells. The memory cell is an electronic circuit that stores one bit ofbinary information and is set to store a logic 1 (e.g. high voltagelevel) or reset to store a logic 0 (e.g. low voltage level). A memorycell is also known as a bit cell. In a Random-Access Memory (RAM) thebit value may be maintained (stored) until it is changed by a set orreset process. In a Read-Only Memory (ROM) the bit value may behard-wired and unchangeable after manufacture, but can be accessed byreading from the memory cell.

A RAM typically stores data as long as power is applied: it is avolatile memory. One type of RAM is an SRAM (Static RAM), which iscalled ‘static’ because no periodic refresh is needed as in a DRAM(Dynamic RAM). An SRAM memory cell has more components and uses morechip space than a DRAM memory cell, but reading from and writing to anSRAM is generally much faster than from a DRAM. For this reason, SRAM istypically used for registers and cache memories.

With reference to FIG. 7 , one implementation of an SRAM bit cellcomprises two cross-coupled inverters that hold the bit value Q (and itscomplement Q′) and two access transistors. The SRAM comprises an arrayof memory cells, with word lines (WL) used to address a row of bit cellsand bit lines (BL and BL) used for reading and writing from an addressedmemory cell. In this example, the bit lines are used differentially,meaning that the difference between the data present on the two bitlines BL and BL is sensed to read the stored data value. This optionaldifferential technique is useful for large memories having long linesconnected to many memory cells in each column and are typically providedin order to improve noise margins.

A typical implementation of an SRAM memory cell uses six transistors inthe form of MOSFETs, such as the example shown in FIG. 8 . The datastored in the memory cell is stored using four transistors M1, M2, M3,M4 that form the two cross-coupled inverters of FIG. 7 . For example, M1and M3 may be NMOS MOSFETs and M2 and M4 may be PMOS MOSFETs. Thismemory cell has two stable states which are used to denote 0 and 1. Twoadditional access transistors M5 and M6 serve to control access to thememory cell during read and write operations. M5 and M6 may be NMOSMOSFETs.

Access to the memory cell is enabled by the word line (WL in FIG. 8 )which controls the two access transistors M5 and M6 which, in turn,control whether the memory cell should be connected to the bit lines BLand BL, which are used to transfer data for both read and writeoperations. A single bit lines could also be used. During read accesses,the bit lines are actively driven high and low by the inverters in theSRAM memory cell. This improves SRAM bandwidth compared to e.g. DRAMs inwhich each bit line is connected to storage capacitors and chargesharing causes the bit line to swing upwards or downwards. The symmetricstructure SRAMs also allows for differential signaling, which makessmall voltage swings more easily detectable. Another factor thatcontributes to making SRAM faster than DRAM is that commercial SRAMchips accept all address bits at the same time. By comparison, commodityDRAMs have the address multiplexed in two halves, i.e. higher bitsfollowed by lower bits, over the same package pins in order to keep thechip size and cost down. FIG. 10 shows an example of an SRAM includingmemory cells, word lines and bit lines.

There is always some variability in semiconductor manufacturingprocesses which results in unintended random variations in the resultingsemiconductor devices being manufactured. Any circuit design, whenfabricated in silicon, typically exhibits slightly different electricalbehavior from one chip to another even if the design, mask (in case ofmask based lithography) and fab are identical. This variability formsthe basis of physically unclonable function (PUF) technology which hasbeen proposed for applications with high security requirements, such asauthentication systems. A PUF is an entity embodied in a physicalstructure that is easy to evaluate but hard to predict and almostimpossible to duplicate. PUFs depend on the uniqueness of their physicalmicrostructure which in turn depends on random physical factorsintroduced during manufacturing. These factors are unpredictable anduncontrollable, which makes it virtually impossible to duplicate orclone the structure. PUFs can be used for example as a unique anduntamperable device identifier.

A PUF circuit may be designed to produce a data value, such as acryptographic key. This data value may be a secret that is to beunreadable and undetectable except for a chip embedding the PUF circuit.This chip may have a provision for a challenge-response mechanism thatproves its identity without revealing the underlying cryptographic keyfrom the PUF circuit, or any other provision to use the data value fromthe PUF circuit without revealing the data value to the outside.

An SRAM may be used as a PUF. An SRAM PUF may be made as an intrinsicPUF which uses the random variations in the structures of the memorycells caused by manufacturing process variations as a source ofrandomness. Such an SRAM PUF may be based on the intrinsic mismatchpresent between the two inverters of each SRAM memory cell, which candetermine the value of the data bit stored in each memory cell when theSRAM is powered up (the start-up value of the memory cell). Ideally boththe inverters should be identical, but due to manufacturing variability,there is almost always some random offset between the two inverters. Thestart-up state of an SRAM memory cell is determined by this mismatchwhich is random and virtually unclonable. Typically, a set of startupdata values determined by the start-up state of a set of SRAM cells isused as a PUF, where each cell contributes one bit.

Intrinsic random manufacturing process variations can result invariations in different structures of a typical SRAM memory cell. InSRAM cells, these known variations include intrinsic random dopantfluctuation, intrinsic random line edge and line width roughness, andintrinsic random variations in gate dielectric.

Intrinsic random dopant fluctuation is a source of random processvariation which results from the discreteness of dopant atoms in theactive region of an active circuit element such as a transistor, e.g.variation of doping in the channel of a MOSFET. It is influenced by theposition and number of dopant atoms and has a direct impact on thethreshold voltage of the transistor. With the continuing shrink insemiconductor process node, a small change in the number of dopant atomshas a significant impact. For example, for the 180 μm technology node,there are thousands of dopant atoms in a MOSFET channel, whereas thisnumber has reduced to about 100 atoms for the 32 nm technology node.

Intrinsic random line edge roughness implies a condition wherein thegate of a transistor does not have a constant length or width, becausethe edges of the gate are not straight but rough lines. The deviation ofthe edges from the mean straight line is known as Line Edge Roughness(LER), while the deviation from the mean gate length is known as LineWidth Roughness (LWR).

The high-k gate dielectric used in technologies like the 45 nmtechnology node is highly susceptible to variations in the gatedielectric, such as variations in gate oxide thickness, oxide charges,and interface traps. Intrinsic random physical changes in the dielectricresult in parametric variations in drive current, gate tunnelingcurrent, or threshold voltage of a MOSFET.

A disadvantage of an SRAM PUF which relies on random variations in thestructure of its memory cells caused by random uncontrolledmanufacturing process variations is that the start-up value of the SRAMis random, and can only be determined after manufacture. Furthermore,the start-up value may not be stable, since it relies on small randomvariations which affect the operation of the SRAM inverters, which canbe affected by environmental conditions such as varying temperature orsupply voltage.

A ROM stores data even when no power is applied, it is a non-volatilememory. An example of a ROM is a Mask ROM, which typically consists of agrid of word lines (the address input) and bit lines (the data output),selectively joined together with transistor switches. The Mask ROM canrepresent an arbitrary look-up table with a regular physical layout andpredictable propagation delay.

FIG. 11 shows an example of a Mask ROM. Each memory cell has zero or onetransistor to produce either a binary “1” or a binary “0”. With therelevant address-decoded word line driven with a “1”, the associated bitline will be a “0” if an open-drain transistor with grounded sourceterminal is present; otherwise a pull-up resistor (not shown) holds theoutput at a “1” state.

A disadvantage of Mask ROMs is that the circuit configuration of a MaskROM, and thus the data value stored in the Mask ROM, can be detected byconventional inspection or reverse engineering techniques.

There is a need for a solution wherein the start-up value of a memorydevice can be predetermined without being physically detectable.

It is known that, after a layer of a chip has been created, a doping orimplanting process may be performed to achieve different memory valuesin a ROM. Such known doping or implanting process disadvantageouslyrequires a separate, dedicated process for the implanting of the activeregion. One example hereof is disclosed in US 2016/254269 A1, wherein amemory device includes a plurality of ROM cells each having spaced apartsource and drain regions formed in a substrate with a channel regionthere between, a first gate disposed over and insulated from a firstportion of the channel region, a second gate disposed over and insulatedfrom a second portion of the channel region, and a conductive lineextending over the plurality of ROM cells. The conductive line iselectrically coupled to the drain regions of a first subgroup of the ROMcells, and is not electrically coupled to the drain regions of a secondsubgroup of the ROM cells. Alternately, a first subgroup of the ROMcells each includes a higher voltage threshold implant region in thechannel region, whereas a second subgroup of the ROM cells each lack anyhigher voltage threshold implant region in the channel region. Anotherexample hereof is disclosed in EP 0 991 118A1, wherein a multi-level ROMcan be obtained in a dual gate EEPROM process flow. The method beginswith, on a semiconductor substrate, defining active areas respectivelyfor transistors of ROM cells, transistors of electrically erasablenon-volatile memory cells, and additional transistors of the storagecircuitry. Then, integrated capacitors are integrated in the storagecircuit. According to this method, during the implanting step forforming integrated capacitors, at least an active area of the ROM cellis similarly implanted.

SUMMARY

The disclosed embodiments provide a solution for creating semiconductormemory devices having a start-up data value that can been predeterminedin the production process while begin virtually undetectable usinginspection or reverse engineering techniques. The memory devices can beimplemented in the form of SRAMs or ROMs or other types of memory. Thememory devices can be used as PUFs without being dependent on randommanufacturing variations. The memory devices can be created such that aphysical inspection of the memory cells, e.g. by reverse engineering thememory device using layer removal and electron microscopy does notreveal the measures taken during the production process to set thestart-up data values of the memory cells.

The semiconductor memory device may be embedded in a chip. The start-updata value may be inaccessible from outside of the chip embedding thesemiconductor memory device.

Advantageously, the start-up data value of a memory cell may bepredetermined during manufacturing by varying an exposure dose of one ormore charged particle beams during exposure of the pattern. As a result,the start-up value need not be readable after manufacturing to determinethe value, taking away the need for a readout circuit that may beexploited by an attacker.

Aspects and features of the disclosed embodiments are further describedin the following description and in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying schematic drawings in which correspondingreference symbols indicate corresponding parts, and in which:

FIG. 1 shows a simplified schematic drawing of an exemplary embodimentof a charged particle multi-beamlet lithography system;

FIG. 2 is a conceptual diagram showing an exemplary maskless lithographysystem;

FIG. 3 shows an exemplary functional flow diagram of an embodiment of adata path;

FIGS. 4-6 show exemplary processes of creating a chip;

FIGS. 7-8 are circuit diagrams of exemplary SRAM memory cells;

FIG. 9 is a circuit diagram of an exemplary SRAM;

FIG. 11 is a circuit diagram of an exemplary Mask ROM;

FIGS. 12 a and 12 c show an exemplary SRAM memory cell laid out insilicon;

FIG. 12 b is a legend for FIG. 12 a;

FIG. 13 shows an exemplary tiling of six memory cells of FIG. 12 a;

FIG. 14 shows the features of the poly-silicon layer of FIG. 13 ;

FIG. 15 shows a gate resist on a poly-silicon layer;

FIG. 16 shows a gate resist on a poly-silicon layer after applying adose modulation map;

FIG. 17 shows a circuit diagram of an exemplary Mask ROM includingdefect transistors; and

FIGS. 18 and 19 show the features of the N+ and P+ layer of FIG. 13 andexemplary resist layers for blocking an implantation step.

The figures are intended for illustrative purposes only, and do notserve as restriction of the scope or the protection as laid down by theclaims.

DESCRIPTION OF EMBODIMENTS

FIG. 1 shows a simplified schematic drawing of an exemplary embodimentof a charged particle multi-beamlet lithography machine 1, which may beused for the creation of one or more layers of a transistor based memorycell. Such a lithography machine suitably comprises a beamlet generatorgenerating a plurality of beamlets, a beamlet modulator patterning saidbeamlets into modulated beamlets, and a beamlet projector for projectingsaid beamlets onto a surface of a target. The target is for example awafer. The beamlet generator typically comprises a source and at leastone aperture array. The beamlet modulator is typically a beamlet blankerwith a blanking deflector array and a beam stop array. The beamletprojector typically comprises a scanning deflector and a projection lenssystem.

In the embodiment shown in FIG. 1 , the lithography machine 1 comprisesan electron source 3 for producing a homogeneous, expanding electronbeam 4. Beam energy is preferably maintained relatively low in the rangeof about 1 to 10 keV. To achieve this, the acceleration voltage ispreferably low, the electron source preferably kept at between about −1to −10 kV with respect to the target at ground potential, although othersettings may also be used.

The electron beam 4 from the electron source 3 may pass a doubleoctopole and subsequently a collimator lens 5 for collimating theelectron beam 4. As will be understood, the collimator lens 5 may be anytype of collimating optical system. Subsequently, the electron beam 4may impinge on a beam splitter, which is in one suitable embodiment anaperture array 6A. The aperture array 6A may block part of the beam andmay allow a plurality of subbeams 20 to pass through the aperture array6A. The aperture array preferably comprises a plate havingthrough-holes. Thus, a plurality of parallel electron subbeams 20 may beproduced.

A second aperture array 6B may create a number of beamlets 7 from eachsubbeam. Beamlets are also being referred to as e-beams. The system maygenerate a large number of beamlets 7, preferably about 10,000 to1,000,000 beamlets, although it is of course possible to use more orless beamlets. Note that other known methods may also be used togenerate collimated beamlets. This allows the manipulation of thesubbeams, which turns out to be beneficial for the system operation,particularly when increasing the number of beamlets to 5,000 or more.Such manipulation is for instance carried out by a condenser lens, acollimator, or lens structure converging the subbeams to an opticalaxis, for instance in the plane of the projection lens.

A condenser lens array 21 (or a set of condenser lens arrays) may beincluded behind the subbeam creating aperture array 6A, for focusing thesubbeams 20 towards a corresponding opening in the beam stop array 10. Asecond aperture array 6B may generate beamlets 7 from the subbeams 20.Beamlet creating aperture array 6B is preferably included in combinationwith the beamlet blanker array 9. For instance, both may be assembledtogether so as to form a subassembly. In FIG. 1 , the aperture array 6Bproduces three beamlets 7 from each subbeam 20, which strike the beamstop array 10 at a corresponding opening so that the three beamlets areprojected onto the target by the projection lens system in the endmodule 22. In practice a much larger number of beamlets may be producedby aperture array 6B for each projection lens system in end module 22.In one embodiment, 49 beamlets (arranged in a 7×7 array) may begenerated from each subbeam and are directed through a single projectionlens system, although the number of beamlets per subbeam may beincreased to 200 or more.

Generating the beamlets 7 stepwise from the beam 4 through anintermediate stage of subbeams 20 has the advantage that major opticaloperations may be carried out with a relatively limited number ofsubbeams 20 and at a position relatively remote from the target. Onesuch operation is the convergence of the subbeams to a pointcorresponding to one of the projection lens systems. Preferably thedistance between the operation and the convergence point is larger thanthe distance between the convergence point and the target. Mostsuitably, use is made of electrostatic projection lenses in combinationherewith. This convergence operation enables the system to meetrequirements of reduced spot size, increased current and reduced pointspread, so as to do reliable charged particle beam lithography atadvanced nodes, particularly at nodes with a critical dimension of lessthan 90 nm.

The beamlets 7 may next pass through an array of modulators 9. Thisarray of modulators 9 may comprise a beamlet blanker array having aplurality of blankers, which are each capable of deflecting one or moreof the electron beamlets 7. The blankers may more specifically beelectrostatic deflectors provided with a first and a second electrode,the second electrode being a ground or common electrode. The beamletblanker array 9 constitutes with beam stop array 10 a modulating device.On the basis of beamlet control data, the modulating means 8 may add apattern to the electron beamlets 7. The pattern may be projected ontothe target 24 by means of components present within an end module 22.

In this embodiment, the beam stop array 10 comprises an array ofapertures for allowing beamlets to pass through. The beam stop array, inits basic form, may comprise a substrate provided with through-holes,typically round holes although other shapes may also be used. In oneembodiment, the substrate of the beam stop array 8 is formed from asilicon wafer with a regularly spaced array of through-holes, and may becoated with a surface layer of a metal to prevent surface charging. Inone embodiment, the metal may be of a type that does not form anative-oxide skin, such as CrMo.

In one embodiment, the passages of the beam stop array 10 may be alignedwith the holes in the beamlet blanker array 9. The beamlet blanker array9 and the beamlet stop array 10 typically operate together to block orlet pass the beamlets 7. If beamlet blanker array 9 deflects a beamlet,it will not pass through the corresponding aperture in beamlet stoparray 10, but instead will be blocked by the substrate of beamlet blockarray 10. But if beamlet blanker array 9 does not deflect a beamlet thenit will pass through the corresponding apertures in beamlet stop array10 and will then be projected as a spot on a target surface 13 of thetarget 24.

The lithography machine 1 may furthermore comprise a data path forsupplying beamlet control data, e.g. in the form of pattern bitmap data,to the beamlet blanker array 9. The beamlet control data may betransmitted using optical fibers. Modulated light beams from eachoptical fiber end may be projected on a light sensitive element on thebeamlet blanker array 9. Each light beam may hold a part of the patterndata for controlling one or more modulators coupled to the lightsensitive element.

Subsequently, the electron beamlets 7 may enter the end module.Hereinafter, the term ‘beamlet’ refers to a modulated beamlet. Such amodulated beamlet effectively comprises time-wise sequential portions.Some of these sequential portions may have a lower intensity andpreferably have zero intensity—i.e. portions stopped at the beam stop.Some portions may have zero intensity in order to allow positioning ofthe beamlet to a starting position for a subsequent scanning period.

The end module 22 is preferably constructed as an insertable,replaceable unit, which comprises various components. In thisembodiment, the end module may comprise a beam stop array 10, a scanningdeflector array 11, and a projection lens arrangement 12, although notall of these need be included in the end module and they may be arrangeddifferently.

After passing the beamlet stop array 10, the modulated beamlets 7 maypass through a scanning deflector array 11 that provides for deflectionof each beamlet 7 in the X- and/or Y-direction, substantiallysubstantially perpendicular to the direction of the undeflected beamlets7. In this embodiment, the deflector array 11 may be a scanningelectrostatic deflector enabling the application of relatively smalldriving voltages.

Next, the beamlets may pass through projection lens arrangement 12 andmay be projected onto a target surface 24 of a target, typically awafer, in a target plane. For lithography applications, the targetusually comprises a wafer provided with a charged-particle sensitivelayer or resist layer. The projection lens arrangement 12 may focus thebeamlet, for example resulting in a geometric spot size of about 10 to30 nanometers in diameter. The projection lens arrangement 12 in such adesign for example provides a demagnification of about 100 to 500 times.In this preferred embodiment, the projection lens arrangement 12 isadvantageously located close to the target surface.

In some embodiments, a beam protector may be located between the targetsurface 24 and the focusing projection lens arrangement 12. The beamprotector may be a foil or a plate, provided with needed apertures, forabsorbing the resist particles released from the wafer before they canreach any of the sensitive elements in the lithography machine.Alternatively or additionally, the scanning deflection array 9 may beprovided between the projection lens arrangement 12 and the targetsurface 24.

Roughly speaking, the projection lens arrangement 12 focuses thebeamlets 7 to the target surface 24. Therewith, it further ensures thatthe spot size of a single pixel is correct. The scanning deflector 11may deflect the beamlets 7 over the target surface 24. Therewith, itneeds to ensure that the position of a pixel on the target surface 24 iscorrect on a microscale. Particularly, the operation of the scanningdeflector 11 needs to ensure that a pixel fits well-n- into a grid ofpixels which ultimately constitutes the pattern on the target surface24. It will be understood that the macroscale positioning of the pixelon the target surface is suitably enabled by a wafer positioning systempresent below the target 24.

Such high-quality projection may be relevant to obtain a lithographymachine that provides a reproducible result: Commonly, the targetsurface 24 comprises a resist film on top of a substrate. Portions ofthe resist film may be chemically modified by application of thebeamlets of charged particles, i.e. electrons. As a result thereof, theirradiated portion of the film may be more or less soluble in adeveloper, resulting in a resist pattern on a wafer. The resist patternon the wafer may subsequently be transferred to an underlying layer,i.e. by implementation, etching and/or deposition steps as known in theart of semiconductor manufacturing. Evidently, if the irradiation is notuniform, the resist may not be developed in a uniform manner, leading tomistakes in the pattern. Moreover, many of such lithography machinesmake use of a plurality of bean/lets. No difference in irradiation oughtto result from deflection steps.

FIG. 2 shows a conceptual diagram of an exemplary charged particlelithography system 1A, divided into three high level sub-systems: awafer positioning system 25, an electron optical column 20, and datapath 30. The wafer positioning system 25 moves the wafer 24 under theelectron optical column 20 in the x-direction. The wafer position system25 may be provided with synchronization signals from the data pathsub-system 30 to align the wafer with the electron beamlets generated bythe electron-optical column 20. The electron-optical column 20 mayinclude the charged particle multi-beamlet lithography machine 1 asshown in FIG. 1 . Switching of the beamlet blanker array 9 may also becontrolled via the data path sub-system 30, using pattern bitmap data.

FIG. 3 shows an exemplary functional flow diagram of an embodiment of adata path. In FIG. 3 the functional flow diagram is split into foursections: 3010 is used to indicate a data format of underlying dataoutputs/inputs; 3020 shows the process flow including dataoutputs/inputs (parallelograms) and functional elements (rectangles);3030 is used to indicate process steps performed at overlying functionalelements; and 3040 is used to indicate how often the process steps aretypically performed, e.g. once per design 3041, once per wafer 3042 oronce per field 3043. Roman I, II and III indicate when the feature dataset and/or the selection data may be provided to the data path.

Input to the process may be GDS-II design layout data 2007, or a designlayout in any other suitable format such as an OASIS data format,defining the chip design to be created using the charged particlelithography machine. A pattern data processing system may preprocess1022 the GDS-II file, e.g. once per design as indicated by the arrow3041 at the bottom.

The processes within the dashed block, i.e. from software processing1071A until hardware processing 1073 are typically performed at thelithography machine 1, 1A enabling a more secure operating environment.

Optionally, a chip design part not part of the GDS-II design may beinserted into the pattern data at various stages in the functional flow,indicated by roman I, II and III.

The optional chip design part may be inserted into the pattern data uponprocessing of the design layout data input, in this example GDSII input,indicated by roman I. At this stage the pattern data processing istypically performed in a vector based data format. More preferably theinsertion of the optional chip design part into the pattern data may beperformed at the software processing stage 1071A as indicated by romanII, or at the streaming stage 1071B as indicated by roman III. The S/Wprocessing stage 1071A is typically performed once per wafer, asindicated by the second arrow 3042 from the bottom. The streaming stage1071B is typically performed once per field or once per chip, asindicated by the third arrow 3043.

The S/W processing stage 1071A and the streaming stage 1071B may beimplemented at a pattern streamer. The hardware processing stage 1073 onthe right side of the functional flow typically involves the blankerbeing controlled by the pattern data 2009 including the chip design tobe created.

The GDS-II format pattern data may undergo off-line processing 1022,typically including proximity effect correction, resist heatingcorrection, and/or smart boundaries (jointly depicted 3031). Theresulting corrected vector pattern data 2008 may be in a vector formatan may include dose information, depicted as 3011. This off-lineprocessing 1022 is usually performed once for a given pattern design,for one or more batches of wafers. In case of inserting an optional chipdesign part at this stage, indicated by roman I, the off-line processing1022 may need to be performed more frequently, up to once per wafer oreven once per field or chip

Next, in-line processing of the vector tool input data 2008 may beperformed to rasterize the vector data 2008 to generate pattern systemstreamer (PSS) bitmap data 3021 in e.g. a 4-bit greyscale bitmap format3012.

This processing is typically performed in software. The optional chipdesign part may be added at this stage, as indicated by roman II. Thepattern streamer may then processes the PSS format data 3021 to generateblanker format data 2009, possibly including corrections involving afull or partial pixel shift in the X and/or Y direction for beamposition calibration, field size adjustment, and/or field positionadjustment as before on the bitmap data, jointly depicted 3032.Alternatively to entry point II, the optional chip design part may beadded at this stage as indicated by roman III. This processing may beperformed per field. The blanker format pattern data 2009 may then betransmitted 3022 to the lithography system for exposure of the wafer.

As indicated in FIG. 3 , rasterization may be performed at the streamingstage 1071B, which typically involves real-time processing performed inhardware. Corrections for beam position calibration, field sizeadjustment, and/or field position adjustment 3032 may be performed onvector format PSS format data 3021, and then rasterization may convertthis to a blanker format 2009. When the corrections are made on vectordata, both full pixel shifts and subpixel shifts in the X and Ydirection can be made.

For illustrative purposes, FIGS. 4-6 show examples of processes forfabricating conducting vias for interconnecting two conducting layers ofthe chip. In a similar manner layers other than a via layer may becreated. For example, resist layers may be created before the creationof polysilicon gates or before implanting PMOS or NMOS areas. In otherexamples, a semiconductor layer may be created for transistors ordiodes, a contact layer may be created by forming connections between ametal layer and a gate, and/or a metal layer may be created by formingconnections between circuit elements.

FIG. 4 shows an exemplary process of creating a chip. In this example afirst part of the chip (the left part in FIG. 4 ) may be created usingphotolithography (using a mask) and a second part of the chip (the rightpart in FIG. 4 ) may be created using charged particle multi-beamletlithography (without a mask). At the beginning of the process of FIG. 4the wafer may comprise a bottom metal layer 201 which has beenpreviously patterned to form conductive connecting lines and aninsulating layer 202 (for example SiO2) with resist 205 (e.g. KrFresist) on top as shown in FIG. 4A.

For the creation of the first part, the resist 205 may undergo amask-based exposure, e.g. using a KrF laser, followed by a developmentstep wherein patterns defined by the mask are removed from the resistlayer 205, as shown in FIG. 4B. In an etching and stripping step thesepatterns may be etched into the insulating layer 202 and the resist isthen removed, as shown in FIG. 4C.

Next, a conductive layer 207 may be applied onto the etched and strippedinsulating layer, as shown in FIG. 4D. For example a chemical vapordeposition with Tungsten (CVD-W) may be used, as shown in FIG. 4D.Chemical-mechanical planarization (CMP) may be used to removesuperfluous conductive material resulting in the wafer having the bottommetal layer 201 and a layer 202 comprising insulating material withconductive material present in the locations where conductive vias aredesired, as defined by the mask exposure, shown in FIG. 4E.

Next, for the creation of the second part, the wafer may receive one ormore etch barrier films for etching the insulating layer 202. Forexample, a spin on carbon (SOC) film 203 and a silicon-containingantireflective coating (SiARC) hard mask 204, with an e-beam resist 206formed on top, covering the insulating layer 202 including the etchedpart from the mask-based photolithography phase, as shown in FIG. 4F.The resist 206 may undergo a maskless e-beam exposure followed by adevelopment step wherein patterns exposed by the e-beams are removedfrom the resist 206, as shown in FIG. 4G. In an etching and strippingstep these patterns may be etched into the etch barrier films 203 and204, and the resist may be removed, as shown in FIG. 4H. Next, thepatterns that are created in etch barrier films 203, 204 may be etchedinto the insulating layer 202, and films 203, 204 may be stripped, asshown in FIG. 4I.

Next, a conductive layer 207 may be applied onto the etched and strippedinsulating layer 202, as shown in FIG. 4J. For example a chemical vapordeposition with Tungsten (CVD-W) may be used. Chemical-mechanicalplanarization (CMP) may remove superfluous conductive material, as shownin FIG. 4K, resulting in the wafer having a bottom metal layer 201 and alayer 202 comprising insulating material with conductive materialpresent in the locations where conductive vias are desired, as definedby the mask exposure and the maskless exposure, as shown in FIG. 4K.

In the embodiment of FIG. 4 two CMP steps may be needed. Dishing anddouble erosion effects caused by the CMP steps can affect the thicknessof the insulating layer including the conductive material of the vias.This can have a negative impact on analogue and radio frequencyperformance of the chip. FIG. 5 shows an improved process for creatingchips wherein only a single CMF step may be needed.

FIG. 5 shows another exemplary process of creating a chip. In thisexample a first part (left in FIG. 5 ) of the chip may be created usingmask-based photolithography and a second part (right in FIG. 5 ) of thechip may be created using maskless charged particle multi-beamletlithography.

At the beginning of the process of FIG. 5 the wafer may comprise abottom metal layer 201 which has been previously patterned to formconductive connecting lines, and an insulating layer 202 (for exampleSiO2), under etch barrier films 203 and 204 (e.g. SOC+SiARC HM) and aresist 205 (e.g. KrF resist), as shown in FIG. 5A. Advantageously, theetch barrier films 203 and 204 may be used for both the mask-basedphotolithography and the maskless charged particle multi-beamletlithography phase, thereby eliminating the need for a CMP step in thephotolithography phase, as will be further explained below.

For the creation of the first part, the resist 205 may undergo a maskexposure, e.g. using KrF laser, followed by a development step whereinpatterns defined by the mask may be removed from the resist 205, asshown in FIG. 5B. In an etching and stripping step these patterns may beetched into the SOC 204 and the resist is removed, as shown in FIG. 5C.

Next, for the creation of the second part, the wafer may receive ane-beam resist 206, covering the etch barrier films 203 and 204 includingthe etched part from the photolithography phase, as shown in FIG. 5D.The resist 206 may undergo an e-beam exposure followed by a developmentstep wherein patterns defined by the e-beams may be removed from theresist 206, as shown in FIG. 5E. In an etching and stripping step thesepatterns may be etched into the etch barrier films 203, 204 and theresist 206 is removed, as shown in FIG. 5F. Next, the patterns createdin the etch barrier films 203, 204 in both the mask-basedphotolithography phase and the maskless charged particle multi-beamletlithography phase may be etched into the insulating layer 202, and thefilms 203, 204 may be stripped as shown in FIG. 5G.

Next, a conductive layer 207 may be applied onto the etched and strippedinsulating layer 202 for both the first part and the second part of thechip, as shown in FIG. 5H. For example a chemical vapor deposition withTungsten (CVD-W; may be used. Chemical-mechanical planarization (CMP)may remove superfluous conductive material resulting in the wafer havingthe bottom metal layer 201 and a layer 202 comprising insulatingmaterial with conductive material at locations defined by the maskexposure and the maskless exposure, as shown in FIG. 5I.

An upper metal layer may be deposited over insulating layer 202 andpatterned to create a second set of conductive connecting lines, so thatthe vias formed in insulating layer 202 function as electricalconnections between the bottom and upper metal layers.

FIG. 6 shows another exemplary process of creating a chip. In thisexample, all or a portion of a first part (left in FIG. 6 ) of the chipas well as a second part (right in FIG. 6 ) of the chip may be createdusing maskless charged particle multi-beamlet lithography.

At the beginning of the process of FIG. 6 the wafer may comprise abottom metal layer 201. which has been previously patterned to formconductive connecting lines, and an insulating layer 202 (for exampleSiO2), under etch barrier films 203 and 204 (e.g. SOC+SiARC HM) and ane-beam resist 206 (e.g. KrF resist), as shown in FIG. 10A.

The resist 206 may undergo an e-beam exposure followed by a developmentstep wherein patterns defined by the e-beams may be removed from theresist layer 206, as shown in FIG. 10B. In an etching and stripping stepthese patterns may be etched into the etch barrier films 203, 204 andthe resist 206 may be removed, as shown in FIG. 6C. Subsequently thepatterns may be etched into the insulating layer 202, and the etchbarrier films 203, 204 are stripped, as shown in FIG. 6D.

Next, a conductive layer 207 may be applied onto the etched and strippedinsulating layer 202 for both the first part and the second part of thechip, as shown in FIG. 6E. For example a chemical vapor deposition withTungsten (CVD-W) may be used. Chemical-mechanical planarization (CMP)may remove superfluous conductive material resulting in the wafer havingthe bottom metal layer 201, and a layer comprising insulating materialwith conductive material formed at locations as defined by the e-beams,as shown in FIG. 6F.

The SRAM cell of FIG. 8 may be laid out in silicon as shown in FIG. 12a. The different patterns used in FIG. 12 a are explained in FIG. 12 b.In this example the contact diameter is 90 nm and the smallest gate, asdrawn, is 70 nm. The gate ratios W/L, (width over length) are such thatthe NMOS pull-downs (M1, M3) are stronger than the access transistors(M5, M6). This increases stability during the read cycle, where the bitlines are pre-charged, put in tri-state and then sensed by opening theaccess transistors. In a write cycle one of the inverters' inputs willbe forced low. To take over the value, the PMOS pull-ups (M2, M4) mustbe weaker than the access transistors. PMOS is much weaker than NMOS, sothe geometry can be approximately the same as the access transistors.

FIG. 12 c shows the same 6 T-SRAM bit cell again, indicating exemplarydimensions. The example layout is loosely based on a 0.69 μm² design.Although FIG. 12 c is not perfectly to scale, actual design rules may beas indicated. The design rules in table 1 may further apply.

TABLE 1 design rules Pitch CD/min. Layer (nm) space (nm) Active (OD) 19090/100 Poly (PO) 180 70/110 Contact (CO) 200 90/110 Metal-1 (M1-layer)180 90/90  Via-x, M-x 210 100/110  PO-CO distance 50 — N+/P+ distance190 — Gate after etching 45 —

Note that after etching, the gates become shorter than drawn, e.g. asfollows: L_(silicon)=L_(drawn)−25 nm=45 nm. Also note that the contactsare normally drawn as squares but become round plugs in manufacturing.

The SRAM cells may be tiled onto a wafer for efficient packaging. Anexample hereof is shown in FIG. 13 , wherein six cells of FIG. 12 a witha total of 36 transistors are shown. Adjacent cells are mirrored so thatinterconnects on the boundaries can be shared for efficient use ofspace.

Manufacturing of an SRAM may involve photolithography and/or chargedparticle beam lithography to create the different layers of materialtogether forming the SRAM. Part of the layers form the SRAM cell, forexample as shown in FIG. 12 a. The poly (PO) lines forming the gates ofthe transistors, e.g. the poly lines shown in FIG. 12 a, may be createdusing charged particle beam lithography.

Typically, before creating the gates of the transistors of an SRAM cell,the n-Well, p-Well, and n-Channel, p-Channel and Gate oxide film of then-MOS and p-MOS transistors may have been created. Next, a poly-silicon(polycrystalline silicon) layer may be applied, from which the gateelectrode may formed using the CVD method. Similar to the examples ofFIGS. 4-6 , are e-beam resist may then be applied, possibly includingunder etch barrier films. Using the charged-particle multi-beamletlithography machine, the e-beam resist layer may be exposed, therebycreating the pattern of the gates in the e-beam resist layer. The thuscreated gate resist pattern may be used in a next step to remove thepoly-silicon except for where the gates are to be formed. For example,using the gate resist pattern as a mask, the gate may be formed byetching the poly-silicon. After etching, the resist pattern may beremoved.

Thus, a PO pattern or “gate” pattern such as shown in FIG. 14 may becreated. The pattern in the example of FIG. 14 corresponds with thepattern of the polysilicon layer in FIG. 13 .

It has been found that changing the thickness and/or length of at leasta part of a gate of an inverter transistor of the SRAM cell mayinfluence the start-up value of the SRAM-cell. The dimensions of one ormore gates may thus be changed to achieve a predetermined start-up valueof the SRAM cell. Moreover, charged-particle multi-beamlet lithographyenables creation of gates having different thickness and/or length whilethe different dimensions are within design tolerances. As a result, thedifferent dimensions of the gates are physically undetectable, while thestart-up value of the SRAM cell may be predetermined.

In order to change the width and/or length of the gates of the invertertransistors, a dose modulation map may be applied to the data togenerate beamlet control data 2009, resulting in gate length and/or gatewidth modification at predefined locations. The dose modulation map maybe applied to the data as described for the optional chip design part inthe example of FIG. 3 . The dose modulation map may function as an alphachannel map for alpha composition of the applied doses to pixels on thewafer. The dose modulation map is typically of a lower resolution thanthe pixel size on the wafer. A pixel corresponds for example to a 5.3nm×5.3 nm feature on the wafer, while the resolution of the dosemodulation map may be 42 nm×42 nm.

FIG. 15 shows an example of a part of a gate pattern exposed onto aresist layer, created using a charged-particle multi-beamlet lithographymachine. In this example, the shape of the pattern exposed onto theresist is for forming the gate for a MOSFET in an underlying polysiliconlayer. A grid with cells of 42 nm×42 nm is shown superimposed over theexposed gate pattern (the grid is not present on the wafer but merelyindicates the location of the dose modulation map cells). In the exampleof FIG. 15 , the exposed gate pattern is formed based on pattern dataused to control the charged particle beams, and no dose modulation mapis applied. After the exposure, in a next processing step thepolysilicon may be removed, except where the resist is present on top ofthe polysilicon, to form the gate of the MOSFET.

FIG. 16 shows an example of a result of a dose modulation map beingapplied to the data. The dose modulation map may define that at thelocations DM (depicted as dashed blocks) covering two 42 nm×42 nm gridelements, the resist is to be exposed with the same pattern data as inFIG. 15 but with a higher exposure dose of the charged particle beams,e.g. a 20% increase in exposure dose relative to the other grid elementsof the does modulation map. Exposure dose modifications may be usedwithin the range of −100% and +100%. As a result, after exposure thegate pattern exposed on the resist layer may be slightly smaller at thelocations DM, visualized by the curved shape producing a reduced widthof the gate pattern. Removal of the polysilicon in a next processingstep may thus result in a gate having a (slightly) smaller dimension atthe two grid elements.

The thus changed dimensions of the gate may be designed to influence thestart-up value of an SRAM memory cell. The dimensions (such as widthand/or length) of one or more gates may thus be changed in this way toachieve a predetermined start-up data value which appears in the memorycells when power is applied to the memory device. Variation of theexposure dose using charged-particle lithography with exposure dosevariation enables creation of a circuit design having a large number oftransistor gates, where selected ones of the gates have a differentdimensions, size, or geometry in order to affect the start-up data valuestored in the memory device. The variation in gate dimensions may bekept within the usual design tolerances of the memory device, i.e.within the usual random variations resulting from the variability of themanufacturing process. In this way, the intended variations arevirtually indistinguishable from unintended random variations, andreverse engineering of the memory device becomes very difficult, whilethe start-up value of the memory device may be predetermined.

In a similar manner, dimensions of other structures in the memory devicemay be altered in a manner which generates a predetermined start-up datavalue in the memory device while being very difficult to detect.

In an alternative embodiment, the gate features may be written usingmulti-beam vector writing. In this embodiment the dimensions of a gatemay be locally changed to achieve a predetermined start-up value of theSRAM cell by changing the vector pattern or by changing the time/doseper pixel during the vector writing process.

According to another aspect of the disclosed embodiments, thecharged-particle multi-beamlet lithography machine may be used to createa resist layer prior to doping or implanting NMOS or PMOS active areas.It is known that a resist layer is applied to cover a PMOS area whenimplanting an NMOS area, and vice versa that a resist layer is appliedto cover a NMOS area when implanting a PMOS area. A PMOS transistor canbe intentionally made non-functional by not covering the PMOS area ofthe transistor during NMOS implantation (for other NMOS transistors),and an NMOS transistor can be intentionally made non-functional by notcovering the NMOS area of the transistor during PMOS implantation. Thelevel of doping in an active area (e.g. PMOS or NMOS area) of atransistor is very difficult to detect by physical inspection of asemiconductor device. In order to make detection of the non-functioningtransistors even harder to detect, the portion of the PMOS or NMOS arealeft uncovered may small, resulting in only a small area of incorrectimplantation while still achieving a non-functional transistor.

Such physically undetectable non-functional transistors may be used tocreate physically obfuscated ROMs or other memory devices, wherein thememory cells are created such that a physical inspection of the memorycell, e.g. by reverse engineering the memory chip using layers removaland electron microscopy, does not reveal the measures taken during theproduction process to predetermine the start-up data values in thememory cells. In the case of ROM memory cells, the start-up data valueof a memory cell typically corresponds with the intended ROM content.

In FIG. 17 a part of an exemplary physically obfuscated ROM isschematically visualized, wherein from the outside all bit lines andword lines appear to be connected to transistors, hence the ROM would befilled with binary “0” values. In fact, the transistors depicted “X”have been created using the above described method, wherein PMOS and/orNMOS areas have been incorrectly implanted and therefore are defective.The ROM of FIG. 17 operates as if it were a ROM as shown in FIG. 11 .Thus, in the example of FIG. 17 the data content of the ROM isdetermined by the working transistors and non-functional transistors,where a non-functional transistor results in a binary “1” (as if thereis no transistor present) and a working transistor results in a binary“0”.

Alternatively, a ROM content may be determined using a diode matrix, inwhich case the data content of the ROM may be determined by workingdiodes and non-functional diodes, where a non-functional diode resultsin a binary “1” (as if there is no diode present) and a working dioderesults in a binary “0”. Herein, a non-functional diode may be realizedin a similar manner as described for the non-functional transistor.

In a similar manner, inverter transistors of SRAM memory cells may bemade non-functional in a physically virtually undetectable manner,thereby influencing the start-up data value of the SRAM memory cell.

When the design of a memory device is defined by pattern data to be usedin charged particle lithography for making the memory device, anexposure dose modulation map may be applied to the pattern data toachieve that parts of the resist layer are opened to enable incorrectimplantation of NMOS or PMOS areas, depending on the implantation phase.The dose modulation map may be applied to the pattern data as describedfor the optional chip design part in the example of FIG. 3 . In thiscase the dose modulation map may be used to set the exposure dose to100% at predefined locations, thereby creating openings in the resistlayer and allowing a next implantation step to provide doping throughthe openings to create non-functional transistors.

FIG. 18 shows N+ and P+ features in NMOS and PMOS areas of transistorsin a SRAM cell, similar to FIG. 12 a. In the example of FIG. 18 , aresist layer RL has been patterned using charged-particle multi-beamletlithography. The resist layer RL covers the two NMOS areas. In theresist layer an opening has been created by the patterning to allowtransistor M1, which is located underneath the opening in the example ofFIG. 12 a, to become non-functional after the implanting step of thePMOS areas. The opening may be created using an exposure dose modulationmap, as described above. Instead of one opening, multiple openings maybe created in the resist layer. The openings can have any shape.

FIG. 19 shows an alternative method for creating non-functionaltransistors. In FIG. 19 the area that is intended to be implanted ispartly covered by the resist layer. As a result the implantation may beinsufficient and a transistor may be non-functional as a result. FIG. 19is similar to FIG. 18 . FIG. 19 shows N+ and P+ features in NMOS andPMOS areas of transistors in a SRAM cell, similar to FIG. 12 a. In theexample of FIG. 19 a resist layer RL has been patterned usingcharged-particle multi-beamlet lithography. The resist layer RL coversthe two NMOS areas. Furthermore, resist covers a part of the PMOS areathat is to be implanted. In this example, an active region of transistorM2 (see also the example of FIG. 12 a ) has been covered by the resistlayer, indicated by the additional resist. After the implanting step ofthe PMOS area, the active region may have received insufficient dopingbecause of the covered portion, resulting in transistor M2 beingnon-functional. The additional resist may have been created using anexposure dose modulation map, in this case indicating for the additionalresist area that a zero exposure dose is to be applied to the resistlayer in the patterning step. Instead of one additional resist area,multiple additional resist areas may be created in the resist layer. Theadditional resist can have any shape.

The method of FIG. 18 and the method of FIG. 19 may be combined.

The embodiments may further be described using the following clauses:

1. A method for making a semiconductor memory device comprising aplurality of memory cells for storing one or more data values, themethod comprising:

-   -   exposing a pattern on a wafer for creating structures for a        plurality of memory cells for the semiconductor memory device,        the structures comprising one or more common features of a        plurality of the memory cells, wherein the pattern is exposed by        means of one or more charged particle beams in a maskless        pattern writer; and    -   varying an exposure dose of the one or more charged particle        beams during exposure of the pattern to generate a set of one or        more non-common features in one or more structures of at least        one of the memory cells, so that the structures of the at least        one memory cell differ from the corresponding structures of        other memory cells of the semiconductor memory device.        2. The method according to clause 1, wherein the semiconductor        memory device stores an initial data value, the initial data        value being determined at least in part by the set of non-common        features of the semiconductor memory device.        3. The method according to clause 1, wherein the semiconductor        memory device generates an initial data value in one or more of        the memory cells upon power-up of the semiconductor memory        device, the initial data value being determined, at least in        part by the set of non-common features of the semiconductor        memory device.        4. The method according to any one of clauses 1-3, wherein the        pattern exposed on the wafer is essentially the same for each        memory cell of the plurality of memory cells, except for the        exposure dose variation.        5. The method according to any one of clauses 1-4, wherein the        set of non-common features include a gate of a transistor        forming part of one of the memory cells of the semiconductor        memory device, and wherein the varying of the exposure dose of        the one or more charged particle beams during exposure of the        pattern creates a variation in a width and/or a length of the        gate without removing the gate.        6. The method according to any one of clauses 1-5, wherein the        set of non-common features include an active region of a        transistor or diode forming part of one of the memory cells of        the semiconductor memory device, and wherein the varying of the        exposure dose of the one or more charged particle beams during        exposure of the pattern creates one or more openings in a resist        layer covering the active area, wherein the openings result in a        variation in an N+ or P+ doping of the active region of the        transistor in a subsequent doping process.        7. The method according to clause 6, wherein the transistor or        diode of the semiconductor memory device is non-functional as a        result of the variation of the N+ or P+ doping of the active        region of the transistor.        8. The method according to any one of clauses 1-7, wherein the        dose variation is derived from application of a dose modulation        map to design layout related data used to prepare, pattern data        for controlling the charged particle beams.        9. The method according to clause 8, wherein the dose modulation        map defines a relative change in a dose to be applied at a        predefined portion of the pattern.        10. The method according to clause 8, wherein the dose        modulation map defines an absolute dose to be applied at a        predefined portion of the pattern.        11. The method according to any one of clauses 1-10, wherein the        exposure dose variation results in variation of the set of        non-common features within manufacturing tolerances of the        feature.        12. The method according to any one of the clauses 1-11, wherein        the semiconductor memory device is an SRAM or ROM.        13. The method according to any one of the clauses 1-12, further        comprising incorporating the semiconductor memory device into a        package to form a semiconductor chip.        14. The method according to any one of clauses 1-13, further        comprising making a plurality of additional semiconductor memory        devices, each semiconductor memory device made according to        clause 1.    -   wherein the semiconductor memory device and the additional        semiconductor memory devices form a set, wherein each        semiconductor memory device of the set has a same number of        memory cells as the other semiconductor memory devices of the        set, and the memory cells of each semiconductor memory device of        the set has a same structure as the memory cells of all of the        other semiconductor memory devices of the set except for the        non-common features,    -   wherein the set of semiconductor memory devices comprises a        plurality of subsets of semiconductor memory devices, each        semiconductor memory device of the set being a member of only        one of the subsets, and    -   wherein the set of non-common feature of the semiconductor        memory devices in a subset is the same, and is different from        the set of non-common features of the semiconductor memory        devices in every other subset.        15. The method according to clause 14, wherein each        semiconductor memory device of the set generates an initial data        value upon power-up, the initial data value being determined at        least in part by the set of non-common features of the        semiconductor memory device.        16. The method according to clause 15, wherein the initial data        value of each semiconductor memory device in a subset is the        same, and is different from the initial data value of the        semiconductor memory devices in every other subset.        17. A semiconductor memory device formed using the method        according to any one of the clauses 1-16.        18. A semiconductor memory chip device from by making a        semiconductor memory device using the method according to any        one of the clauses 1-16, and incorporating the semiconductor        memory device into a package to form the semiconductor chip.        19. A semiconductor memory device comprising a plurality of        memory cells for storing one or more data values,    -   wherein the semiconductor memory device is a member of a set of        semiconductor memory devices,    -   wherein each semiconductor memory device of the set has a same        number of memory cells as all of the other semiconductor memory        devices of the set, and the memory cells of each semiconductor        memory device of the set has a same structure as the memory        cells of all of the other semiconductor memory devices of the        set except for a set of one or more non-common features,    -   wherein the set of semiconductor memory devices comprises a        plurality of subsets of semiconductor memory devices, each        semiconductor memory device of the set being a member of only        one of the subsets,    -   wherein the semiconductor memory device stores an initial data        value upon power-up of the semiconductor memory device,    -   wherein the initial data value is determined at least in part by        the set of non-common features of the semiconductor memory        device, and    -   wherein the initial data value of the semiconductor memory        device is the same as the initial data value of the        semiconductor memory devices in each subset and is different        from the initial data value of the semiconductor memory devices        in every other subset.        20. The semiconductor memory device according to clause 19,        wherein the set of non-common features includes a gate of a        transistor forming part of one of the memory cells of the        semiconductor memory device, and wherein a width and/or a length        of the gate is the same as a corresponding width and/or length        of the gate of a corresponding transistor of the semiconductor        memory devices in each subset, and is different from a        corresponding width and/or length of the gate of a corresponding        transistor of the semiconductor memory devices in every other        subset.        21. The semiconductor memory device according clause 19 or 20,        wherein the set of non-common features includes an active region        of a transistor forming part of one of the memory cells of the        semiconductor memory device, wherein an N+ or P+ doping of the        active region is the same as a corresponding active region of a        corresponding transistor of the semiconductor memory devices in        each subset, and is different from a corresponding active region        of a corresponding transistor of the semiconductor memory        devices in every other subset.        22. The semiconductor memory device according to clause 21,        wherein the transistor of the semiconductor memory device is        non-functional as a result of the N+ or P+ doping of the active        region of the circuit element.        23. The semiconductor memory device according to any one of        clauses 19-22, wherein the set of non-common features is created        in part by an exposure dose variation of a charged-particle beam        during manufacture of the semiconductor memory device.        24. A maskless pattern writer such as a charged particle        multi-beamlet lithography machine (1), configured to expose a        pattern on a surface of a target such as a wafer for making a        semiconductor memory device using the method according to any        one of the clauses 1-16.        25. A manufacturing facility comprising the maskless pattern        writer according to clause 24.

It will be appreciated that the embodiments of the present disclosureare not limited to the exact construction that has been described aboveand illustrated in the accompanying drawings, and that variousmodifications and changes may be made without departing from the scopethereof. The present disclosure has been described in connection withvarious embodiments, other embodiments of the present disclosure will beapparent to those skilled in the art from consideration of thespecification and practice of the embodiments disclosed herein. It isintended that the specification and examples be considered as exemplaryonly, with examples of the true scope and spirit of the disclosedembodiments being indicated by the following claims.

The descriptions above are intended to be illustrative, not limiting.Thus, it will be apparent to one skilled in the art that modificationsmay be made as described without departing from the scope of the claimsset out below.

1-15. (canceled)
 16. A semiconductor memory device comprising aplurality of memory cells for storing one or more data values, whereinthe semiconductor memory device is a member of a set of semiconductormemory devices, wherein each semiconductor memory device of the set hasa same number of memory cells as all of the other semiconductor memorydevices of the set, and the memory cells of each semiconductor memorydevice of the set has a same structure as the memory cells of all of theother semiconductor memory devices of the set except for a set of one ormore non-common features, wherein the set of semiconductor memorydevices comprises a plurality of subsets of semiconductor memorydevices, each semiconductor memory device of the set being a member ofonly one of the subsets, wherein the semiconductor memory device storesan initial data value upon power-up of the semiconductor memory device,wherein the initial data value is determined at least in part by the setof non-common features of the semiconductor memory device, and whereinthe initial data value of the semiconductor memory device is the same asthe initial data value of the semiconductor memory devices in eachsubset and is different from the initial data value of the semiconductormemory devices in every other subset.
 17. The semiconductor memorydevice according to claim 16, wherein the set of non-common featuresincludes a gate of a transistor forming part of one of the memory cellsof the semiconductor memory device.
 18. The semiconductor memory deviceaccording claim 16, wherein the set of non-common features includes anactive region of a transistor or diode forming part of one of the memorycells of the semiconductor memory device.
 19. (canceled)
 20. (canceled)21. The semiconductor memory device of claim 17, wherein a width and/ora length of the gate is the same as a corresponding width and/or lengthof the gate of a corresponding transistor of the semiconductor memorydevices in each subset, and is different from a corresponding widthand/or length of the gate of a corresponding transistor of thesemiconductor memory devices in every other subset.
 22. Thesemiconductor memory device of claim 18, wherein an N+ or P+ doping ofthe active region is the same as a corresponding active region of acorresponding transistor of the semiconductor memory devices in eachsubset, and is different from a corresponding active region of acorresponding transistor of the semiconductor memory devices in everyother subset.
 23. The semiconductor memory device according to claim 22,wherein the transistor or diode of the semiconductor memory device isnon-functional as a result of the N+ or P+ doping of the active regionof the circuit element.
 24. The semiconductor memory device according toclaim 16, wherein the set of non-common features includes one of aplurality of non-functional transistors and a plurality ofnon-functional diodes.
 25. The semiconductor memory device according toclaim 16, wherein the semiconductor memory device comprises a ROMdevice, and a data content of the ROM device is determined in part bythe set of non-common features.
 26. The semiconductor memory deviceaccording to claim 16, wherein the semiconductor memory device comprisesan SRAM device, and the set of non-common features includes a pluralityof non-functional inverter transistors of the SRAM device.
 27. Thesemiconductor memory device according to claim 16, wherein the set ofnon-common features is created in part by an exposure dose variation ofa charged-particle beam during manufacture of the semiconductor memorydevice.
 28. The semiconductor memory device according to claim 27,wherein the dose variation is derived from application of a dosemodulation map to design layout related data used to prepare patterndata for controlling the charged particle beams.
 29. The semiconductormemory device according to claim 28, wherein the dose modulation mapdefines an absolute dose to be applied at a predefined portion of thepattern.
 30. A maskless pattern writer such as a charged particlemulti-beamlet lithography machine, configured to expose a pattern on asurface of a target such as a wafer for making the semiconductor memorydevice of claim
 16. 31. A semiconductor memory device comprising aplurality of memory cells for storing one or more data values, whereinstructures for the plurality of memory cells comprise one or more commonfeatures of a plurality of the memory cells and a set of one or morenon-common features in one or more of the structures of at least one ofthe memory cells, so that the structures of the at least one memory celldiffer from the corresponding structures of other memory cells of thesemiconductor memory device; wherein the semiconductor memory devicestores an initial data value upon power-up of the semiconductor memorydevice, and wherein the initial data value is determined at least inpart by the set of non-common features of the semiconductor memorydevice.
 32. The semiconductor memory device according to claim 31,wherein the set of non-common features includes a gate of a transistorforming part of one of the memory cells of the semiconductor memorydevice.
 33. The semiconductor memory device according to claim 31,wherein the set of non-common features includes an active region of atransistor or diode forming part of one of the memory cells of thesemiconductor memory device.
 34. The semiconductor memory deviceaccording to claim 33, wherein the transistor or diode is non-functionalas a result of N+ or P+ doping of the active region.
 35. Thesemiconductor memory device according to claim 31, wherein the set ofnon-common features includes one of a plurality of non-functionaltransistors and a plurality of non-functional diodes.
 36. Thesemiconductor memory device according to claim 31, wherein thesemiconductor memory device comprises a ROM device, and a data contentof the ROM device is determined in part by the set of non-commonfeatures.
 37. The semiconductor memory device according to claim 31,wherein the semiconductor memory device comprises an SRAM device, andthe set of non-common features includes a plurality of non-functionalinverter transistors of the SRAM device.